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Lead Reduction Among Combinatorial Logic Circuits

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1 Author(s)
Vilkelis, W.V. ; IBM Data Systems Division laboratory, P.O. Box 390, Poughkeepsie, New York 12602, USA

The paper provides a description of the behavior of lead reduction among combinatorial logic circuits. Methods by which one may design the lead reduction architecture for modular packaging schemes are developed. The methods are then applied to the design of the lead reduction architecture of an integrated circuit chip and a nine-chip cell.

Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.  

Published in:

IBM Journal of Research and Development  (Volume:26 ,  Issue: 3 )

Date of Publication:

May 1982

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