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Influence on LSI Package Wireability of Via Availability and Wiring Track Accessibility

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3 Author(s)
Koch, J.H. ; IBM General Technology Division laboratory, East Fishkill Facility, Hopewell Junction, New York 12533, USA ; Mikhail, W.F. ; Heller, W.R.

In this paper, experiments are reported which use automatic global and line-packing wiring routines, supplemented by a restricted maze runner, to evaluate the overall influences of several important physical variables upon the wireability of several logic-circuit package types. The logic circuits are contained in subpackages (e.g., modules carrying chips), which are inserted, using pins, into the carrier package in a regular array of holes otherwise available as vias interconnecting the wiring planes. Over a range of connection counts from several hundred to several thousand, it is found that “overflows” (connections not wired by the program) amounting to as much as 10 or 15% of the wires can be substantially reduced in number by careful design. This can be done by using a sufficient number of programmable vias (greater than one per used pin) and by using a track grid ensuring maximum global track accessibility to all pins, or by a combination of both of these tactics in conjunction with suitable wiring algorithms. Some simple theoretical arguments are given which characterize the design problem in the light of the results.

Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.  

Published in:

IBM Journal of Research and Development  (Volume:26 ,  Issue: 3 )