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Until recently, the ever-increasing demand for higher device density in integrated-circuit (IC) designs has been satisfied mainly through device and circuit design ingenuity, increased chip size, and dimensional reduction. To keep pace with dimensional reduction, control of dimensional variations has assumed a more significant role. New IC designs are very dense and performance-oriented, requiring 2-µm lithography ground rules with less than ±0.2-µm variations in circuit-feature dimensions at 3σ. Such small variations are difficult to detect and control with the present-day routine in-line-inspection optical tools. In this article, we present a description of the primary causes of dimensional variations in a typical manufacturing environment and proposals for their control.
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