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This paper presents a design for a software system (OYSTER) for the parametric simulation and analysis of the fabrication steps of very large scale integrated circuit devices. The system is based on a solid geometric modeling approach in which the component parts of an integrated circuit are represented at any step as three-dimensional solid objects in a geometric data base. The simulation of a fabrication step transforms the data base representation of the geometry and the relations among component parts from their state before the step to their state after the step. At any step, and particularly after the final step, the component parts may be analyzed automatically to determine geometric, mechanical, thermal, and electrical properties. Statistical effects may be incorporated to allow investigation of alignment tolerance build-up and yield. A prototype study is described in which an existing geometric modeling system is used to transform a set of planar masks for an FET device through 28 process steps into 3-D models which are used to compute device capacitances.
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