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Using a hardware simulation engine for custom MOS structured designs

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4 Author(s)
Barzilai, Z. ; IBM Research Division, P.O. Box 218, Yorktown Heights, New York 10598, USA ; Beece, D.K. ; Huisman, L.M. ; Silberman, G.M.

Mixed-level simulation techniques are widely used in VLSI designs for verification and test evaluation. In this paper we indicate how to perform mixed-level simulation on structured MOS designs using the Yorktown Simulation Engine (YSE), a hardware simulator developed at IBM. On the YSE, simulation can be done at the functional, gate, and transistor levels. The design specification used by the YSE is well suited for mixed-level simulation, particularly with regard to interfacing the different levels. We apply our techniques to an nMOS design to show the important features of our approach.

Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.  

Published in:

IBM Journal of Research and Development  (Volume:28 ,  Issue: 5 )

Date of Publication:

Sept. 1984

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