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Signal processor chip implementation

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1 Author(s)
Beraud, Jean Paul ; IBM France, B.P. 58, 91102 Corbeil-Essonnes, Cedex, France

Very large microprocessors can now be integrated on a single chip; the integration eliminates packaging delays and is especially attractive for performance-oriented processors such as signal processors. This paper describes a semicustom signal processor chip designed jointly by the IBM France Essonnes and La Gaude laboratories. The logic is implemented from an optimized library of bipolar circuits. Layouts are compatible and designed to map data flow structures efficiently. Chip design time has been greatly reduced through the use of developed CAD tools tailored to our methodology. The design achieves twice the density that would be possible (with the same technology) with a masterslice. The chip's high performance has been verified with hardware; it provides enough computation power for 125 second-order filters with 8-kHz sampling of the input signal.

Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.  

Published in:

IBM Journal of Research and Development  (Volume:29 ,  Issue: 2 )

Date of Publication:

March 1985

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