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The effects of wafer to wafer defect density variations on integrated circuit defect and fault distributions

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1 Author(s)
Stapper, C.H. ; IBM General Technology Division, Burlington facility, Essex Junction, Vermont 05452, USA

A method for modeling the variations in defect levels in circuits produced on modern integrated circuit manufacturing lines is described in this paper. The effects on defect and fault distributions are derived. A deficiency in some previous yield models is eliminated.

Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.  

Published in:

IBM Journal of Research and Development  (Volume:29 ,  Issue: 1 )