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Analysis of the holding current in CMOS latch-up

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1 Author(s)
Matino, Haruhiro ; IBM Japan, Ltd. Yamato Laboratory: 1623-14, Shimotsuruma, Yamato-shi, Kanagawa-ken 242, Japan

The holding current in CMOS latch-up with or without well and/or substrate bias has been examined. Measurements indicate that the holding current increases significantly with reverse bias and low shunting base resistance. It is shown that a previous equation for the holding current is inaccurate, and a new equation for holding current with bias is presented.

Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.  

Published in:

IBM Journal of Research and Development  (Volume:29 ,  Issue: 6 )