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Reducing execution parameters through correspondence in computer architecture

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2 Author(s)
Wakefield, Scott P. ; IBM Thomas J. Watson Research Center, P.O. Box 704, Yorktown Heights, New York 10598, USA ; Flynn, M.

The purpose of this study is to develop and extend techniques to provide architectural correspondence between high-level language objects and hardware resources so as to minimize execution time parameters (memory traffic, program size, etc.). A resulting computer instruction set called Adept has been emulated, and a compiler has been developed with it as the target language. Although the study was restricted to Pascal, the resulting data are generally applicable to the execution time environment of any procedure-based language. Data indicate that significant bandwidth reductions are possible compared to System/370, VAX, P-code, etc. Specifically, the average improvement ratios realized were instruction bandwidth reduction: 3.46; data read reduction (in bytes): 5.42; data write reduction (in bytes): 14.72.

Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.  

Published in:

IBM Journal of Research and Development  (Volume:31 ,  Issue: 4 )