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High-resolution lithographic capability is required for the fabrication of fully scaled semiconductor devices at minimum dimensions of 0.5 µm to 0.25 µm—the prototype for the semiconductor logic and memory CMOS devices of the 1990s. Electron-beam exposure tools provide this capability. Fully scaled 0.5-µm test devices were fabricated using a modified EL-3 variable shaped-electron-beam system, while 0.25-µm ground-rule lithography was accomplished with a Gaussian round-electron-beam Vector Scan system. An important part of this technology is the selection of lithographic resist system and the process used for pattern definition and transfer. Twelve or more lithographic steps are often needed for circuit devices with the above minimum dimensions. For fully scaled applications, each one of these pattern levels must be defined by electron-beam lithography, and each level may require a specific lithographic resist. Thus, the electron-beam system and the resist process must be mutually compatible if the required resolution, feature size control, and pattern-level-to-pattern-level overlay accuracy are to be achieved. This paper discusses the successful integration of e-beam lithography and resist technologies and their application to CMOS device fabrication.
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