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Large-area fault clusters and fault tolerance in VLSI circuits: A review

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1 Author(s)
Stapper, C.H. ; IBM General Technology Division, Burlington facility, Essex Junction, Vermont 05452, USA

Fault-tolerance techniques and redundant circuits have been used extensively to increase the manufacturing yield and productivity of integrated-circuit chips. Presented here is a review of relevant statistical models which have been used to account for the effects on manufacturing yield of the large-area defect and fault clusters commonly encountered during chip fabrication. A statistical criterion is described for determining whether such large-area clusters are present.

Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.  

Published in:

IBM Journal of Research and Development  (Volume:33 ,  Issue: 2 )