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This paper describes the boundary-scan and built-in self-test (BIST) functions of the IBM token-ring local area network (LAN) adapter chip. These functions present a number of unique features. First, less that 1% of available standard cell circuits were needed to implement these functions. Second, clocking methods used in different logical macros were merged into a comprehensive clocking sequence for self-test. Finally, asynchronous serial and parallel interfaces were provided to facilitate the communication between a test system and the chip's built-in test circuits. Although self-test and boundary-scan provide for an inexpensive higher-level package test, evaluation showed that automatically generated deterministic patterns provide a better-quality VLSI chip manufacturing test.
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