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Internal probing of submicron FETs and photoemission using individual oxide traps

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2 Author(s)
Restle, P. ; IBM Research Division, Thomas J. Watson Research Center, P.O. Box 218, Yorktown Heights, New York 10598, USA ; Gnudi, A.

In submicron field-effect transistors with channel area less than 0.5 µm2, the capture or emission of a single electron (or hole) in the gate oxide has an easily observable effect on the device resistance. Measurements are described in which the time and amplitude of the resistance change due to each capture and emission event from an individual trap are extracted to obtain the average capture and emission times, and the amplitude of the resistance change, at different temperatures, device biases, and light intensities. Techniques are described for using the data at different biases to characterize the trap, find the location of the trap in the device, and then use the trap as a probe of the oxide field (or surface potential) and the surface charge density within a 5-50-Å radius of the trap. In some devices a single trap can be resolved over almost all designed bias regions of the FET near room temperature. In effect, individual traps can be used as internal probes into VLSI devices of the present and future. Results from 2D computer device modeling of these devices are used to evaluate and understand these techniques. Methods for applying these techniques to the study of device degradation are discussed. Data are presented in which photoemission is observed from a single electron trap.

Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.  

Published in:

IBM Journal of Research and Development  (Volume:34 ,  Issue: 2.3 )