By Topic

Preface

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)

Very-large-scale integrated (VLSI) circuits present some very challenging and interesting problems to the testing community. It is the objective of this special issue to describe and discuss some oft he ingenious ways in which these problems are investigated and solved. Before introducing the papers in this issue, a few general comments on testing are in order. The ability to test the performance of a particular technology underlies the progress in developing that technology. In the case of VLSI, this principle applies at every level of the integration hierarchy, from testing ofin dividual devices to testing of new chip and system complexes. The challenges of VLSI are posited by the increased speed of the devices, their decreasing dimensions, and the increasing chip complexity (number of transistors per chip and number of interconnect levels). A distinction should be made between testing for design verification— i. e., testing a new design (novel layout and/or fabrication), be it at device, chip, or system level, and testing for fabrication integrity—Is the chip or package fabricated as designed, or do its defects come from imperfect fabrication? This is the distinction between testing at the research and development stage and testing at the manufacturing stage. At some stage of the design verification these two testingm odes overlap.

Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.  

Published in:

IBM Journal of Research and Development  (Volume:34 ,  Issue: 2.3 )