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Experimental technology and performance of 0.1-µm-gate-length FETs operated at liquid-nitrogen temperature

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7 Author(s)
Sai-Halasz, G.A. ; IBMResearch Division, Thomas J. Watson Research Center, P.O. Box 218, Yorktown Heights, New York 10598, USA ; Wordeman, M.R. ; Kern, D.P. ; Rishton, S.A.
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An overview is presented of our work to explore the extendibility of the silicon FET technology to the 0.1-µm-gate-length level. Self-aligned, n-channel, polysilicon-gated FETs were designed for operation at 77K, with reduced power-supply voltage. Direct-write electron-beam lithography was used to pattern all levels, while other processing followed established lines. Noteworthy results of the work included the observation of a clear manifestation of velocity overshoot, which contributed to achieving extrinsic transconductances above 940 µS/µm at 0.07-µm gate length. The measured switching delay of ring oscillators which contained 0.1-µm-gate-length devices was as low as 13.1 ps, with simulations showing potential for reduction to below 5 ps. Both the transconductance and the switching times are the best values observed for FETs to date-indicating continuing value in the scaling of FETs to dimensions well beyond those currently used.

Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.  

Published in:

IBM Journal of Research and Development  (Volume:34 ,  Issue: 4 )