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On-chip wiring for VLSI: Status and directions

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2 Author(s)
M. B. Small ; IBM Research Division, Thomas J. Watson Research Center, P.O. Box 218, Yorktown Heights, New York 10598, USA ; D. J. Pearson

The thirty-year history of silicon integrated circuits has resulted in dramatic increases in both the number of devices per chip and circuit speed. A consequence of scaling to submicron dimensions is that the major component of propagation delay will transfer from the devices to the interconnecting “wires.” Additionally, increased integration, together with scaling, leads to a need for more numerous interconnections on a chip and higher current densities. Accommodation to these changes will necessitate the use of new materials arranged in three-dimensional wiring structures which have the ability to make the most effective use of the area of the chip. Generic processing routes to achieve the desired structures are reviewed and examples are presented of two experimental structures with layers of planar wiring and vertical vias between planes. One of these integrates aluminum-alloy wiring with tungsten vias in a silicon dioxide dielectric; the other integrates copper wiring and vias in polyimide dielectric with the goal of minimizing delay due to on-chip wiring.

Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.  

Published in:

IBM Journal of Research and Development  (Volume:34 ,  Issue: 6 )