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The Directory and Trace memory chip is a 7.1Kb static random-access memory with 28-bit field simultaneous compare function and independent read and write 28-bit field addressing. The array is organized as four 64 by 28 subarrays. It incorporates a unique Schottky barrier diode (SBD)-coupled cell with active discharge. As memory cells are reduced in size with each new generation, soft errors become a major concern. One method of providing high soft-error immunity is to operate the memory cell transistors in the saturation region. However, in order to write data into such memory cells, the saturation capacitance in the memory cell transistors must be discharged. In prior art, such a capacitive transistor-saturation discharge was accompanied by increased power consumption and/or delay. Typically, the new data signals themselves are used to overcome this saturation capacitance. In this design a unique SBD-coupled active discharge cell discharges the conducting transistor saturation capacitance before writing new data into the cell. Thus, it enhances the write performance and preserves the high soft-error immunity of the cell.
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