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A four-level VLSI bipolar metallization design with chemical-mechanical planarization

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8 Author(s)
Guthrie, W.L. ; IBM Technology Products, East Fishkill facility, Route 52, Hopewell Junction, New York 12533, USA ; Patrick, W.J. ; Levine, E. ; Jones, H.C.
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A high-performance four-level semiconductor device wiring fabrication process has been developed for bipolar devices in Enterprise System/9000™ (ES/9000™) processors. The reliable interconnection of large numbers of devices on a single integrated circuit chip has been enhanced by planarizing insulators and metals using chemical-mechanical polishing processes, by a novel contact stud structure, and by a Ti-clad Al-Cu metallurgy. This paper describes the structure of the four-level wiring and elements of the process, including the silicon contacts, techniques for depositing metal and oxide to cover features with high aspect ratios, high-temperature fine-line lift-off stencils, and high-density, area array solder terminals.

Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.  

Published in:

IBM Journal of Research and Development  (Volume:36 ,  Issue: 5 )