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To achieve the high reliability and performance required by integrated circuit (IC) chips in IBM Enterprise System/9000™ processors, lithography tool centerline overlay variations between masking levels were specified at ± 0.3% µm and circuit design images were transferred with 5× step-and-repeat photolithography tools. In contrast to data obtained from 1× lithography tools, the level-to-level overlay data which characterize deviations from circuit design rules did not fit a normal distribution, and quality control was not achieved with traditional statistical procedures. A methodology was empirically developed which transformed measured data into worst-case overlay points and approximated the data by a gamma distribution. More than 80% of the worst-case distributions were fit by the gamma distribution. The transformation of chip worst-case overlay data and the quality control testing applicable to 5× step-and-repeat lithography tool processes are described in this paper.
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