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Instruction scheduling in the TOBEY compiler

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1 Author(s)
Blainey, R.J. ; IBM Sofware Solutions, 844 Don Mills Road, Toronto, Ontario, Canada M3C 1V7

The high performance of pipelined, superscalar processors such as the POWER2™ and PowerPC™ is achieved in large part through the parallel execution of instructions. This fine-grain parallelism cannot always be achieved by the processor alone, but relies to some extent on the ordering of the instructions in a program. This dependence implies that optimizing compilers for these processors must generate or schedule the instructions in an order that maximizes the possible parallelism. This paper describes the parts of the TOBEY compiler which address the instruction scheduling issue.

Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.  

Published in:

IBM Journal of Research and Development  (Volume:38 ,  Issue: 5 )

Date of Publication:

Sept. 1994

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