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POWER2 instruction cache unit

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4 Author(s)
Barreh, J.I. ; IBM RISC System/6000 Division, 11400 Burnet Road, Austin, Texas 78758, USA ; Golla, R.T. ; Arimilli, L.B. ; Jordan, P.J.

This paper describes the instruction cache unit (ICU) of the IBM POWER2™ processor, with emphasis on improvements over the original POWER ICU design. The POWER2 ICU incorporates a new compare-branch scheme that minimizes processing time penalties, a second branch processor, increased branch look-ahead capability, and doubled instruction-fetch and instruction- dispatch bandwidth.

Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.  

Published in:

IBM Journal of Research and Development  (Volume:38 ,  Issue: 5 )