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CMOS scaling in the 0.1-µm, 1.X-volt regime for high-performance applications

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14 Author(s)
Shahidi, G.G. ; IBM Research Division, Thomas J. Watson Research Center, P.O. Box 218, Yorktown Heights, New York 10598, USA ; Warnock, J.D. ; Comfort, J. ; Fischer, S.
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Deep-submicron CMOS is the primary technology for ULSI systems. Currently, the state-of-the-art CMOS device has a 0.25-µm effective channel length and operates at 2.5 V. As the CMOS technology is extended into the deep submicron range, it is estimated that the next generation will have a nominal channel length of 0.15 µm with a supply voltage of ≤2 V. In this paper, two potential technologies with application to 1.X-V CMOS are presented. First, a bulk CMOS technology with the nominal channel length of 0.15 µm is described. It is next argued that because of issues related to power dissipation, such a device may face problems when operated at its maximum speed-density potential in high-performance logic chips. CMOS on a silicon-on-insulator (SOI) substrate offers circuits with lower power at the same performance. Such a CMOS technology, with channel lengths down to less than 0.1 µm, is described next. This technology is particularly useful for applications near a 1.0-V supply. We describe, for example, a 512Kb SRAM with an access time of less than 3.5 ns at 1.X V. The clear power-performance advantage of CMOS on SOI over that of CMOS on bulk silicon in the 1.X-V regime makes it the technology of choice for sub-0.25-µm CMOS generations.

Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.  

Published in:

IBM Journal of Research and Development  (Volume:39 ,  Issue: 1.2 )