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Charge-metering sampling circuits and their applications

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1 Author(s)
E. S. Schlig ; IBM Research Division, Thomas J. Watson Research Center, P.O. Box 218, Yorktown Heights, New York 10598, USA

Charge-metering sampling circuits comprise a new CMOS circuit class for sampled analog data applications. They avoid some drawbacks of conventional sampling circuits without the use of operational amplifiers. They lightly load their inputs, may be cascaded without buffering to provide analog pipelining, and avoid charge injection errors. Application to linear and nonlinear digital-to-analog converters (DACs), particularly for active matrix display data line drivers, is detailed. In the display application, the nonlinear charge-metering DACs provide a predetermined nonlinear relationship between digital input and display luminance down to the least significant bit, avoiding compromising color reproduction by the use of a piecewise-linear response. Experimental verification of this new circuit class has included the design and fabrication of a cross section of an integrated CMOS six-bit digital-analog data line driver. Experimental results are presented.

Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.  

Published in:

IBM Journal of Research and Development  (Volume:40 ,  Issue: 6 )