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A two-step computation of cyclic redundancy code CRC-32 for ATM networks

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1 Author(s)
Glaise, R.J. ; IBM Networking Hardware Division, La Gaude Laboratory, 06610, France

In the field of telecommunications, among the numerous cyclic redundancy codes in use, ATM CRC-32 is difficult to compute because it is based on a polynomial of degree 32 that has many more terms (15) than any other CRC polynomial in common use. CRC checking and generation are generally carried out on a per-byte basis, in an attempt to cope with the dramatic increase of the data throughput of higher-speed lines. More calculations are needed to process a new incoming byte of data if the number of terms of the polynomial is large, because more bits of the current intermediate result must be combined to calculate each bit of the next one. This tends to counteract the intrinsic speed advantage of the per-byte computation by requiring that more processing be done at each cycle. This paper describes a method that overrides the intrinsic complexity of the CRC-32 computation. It permits expediting AAL5 messages, which must be segmented into ATM cells, with CRC-32 computed at one end, and reassembled from cells, with CRC-32 checked for data integrity at the destination. The calculation is in two steps: 1) A first division is done on the entire message (until the last cell is received or segmented) by a much simpler polynomial. 2) A second division, on the remainder of the first division by the regular CRC-32 polynomial, is performed only once, in order to obtain the final result.

Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.  

Published in:

IBM Journal of Research and Development  (Volume:41 ,  Issue: 6 )