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Plasma-etching processes for ULSI semiconductor circuits

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15 Author(s)
Armacost, M. ; IBM Microelectronics Division, IBM Semiconductor Research and Development Center, 1580 Route 52, Hopewell Junction, New York 12533, USA ; Hoh, P.D. ; Wise, R. ; Yan, W.
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An overview is presented of plasma-etching processes used in the fabrication of ULSI (ultralarge-scale integrated) semiconductor circuits, with emphasis on work in our facilities. Such circuits contain structures having minimum pattern widths of 0.25 µm and less. Challenges in plasma etching in evolving to such dimensions have come from the implementation of antireflective coatings and thinner, more etch-sensitive photoresists; the increased aspect ratios needed to meet design requirements; the additional hard-mask etching steps needed at levels at which lithography is unsuitable for patterning; and increased selectivity requirements, such as the requirement that contact structures be self-aligning. Future circuit density and performance requirements dictate tighter specifications for linewidth variations permitted across a wafer, microloading effects, and device damage. As a result, plasma-etching systems for critical levels are migrating from traditional multifilm, capacitively coupled low-density-plasma systems to medium- and high-density-plasma systems employing exotic or highly polymerizing chemical species specifically designed for one type of film.

Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.  

Published in:

IBM Journal of Research and Development  (Volume:43 ,  Issue: 1.2 )