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The IBM JBIG-ABIC Verification Suite

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2 Author(s)
Colyer, P.S. ; IBM Microelectronics Division, Burlington facility, Essex Junction, Vermont 05452, USa ; Mitchell, J.L.

The IBM JBIG-ABIC Verification Suite is a newly designed verification suite that contains more than 5000 correctly encoded test images. Previously existing verification images in total and consolidated in an ad hoc suite tested only a small fraction of the algorithm and were inadequate. The IBM JBIG-ABIC Verification Suite provides compatibility testing reference data for the ITU-T/ISO JBIG sequential mode and IBM ABIC image compression standards. In this paper, the test images are described and related to the JBIG and ABIC compression standards and options. The verification suite was used to debug and verify the algorithms in the IBM JBIG-ABIC core that is integrated into the Xionics XipChip imaging microcontrollers.

Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.  

Published in:

IBM Journal of Research and Development  (Volume:42 ,  Issue: 6 )

Date of Publication:

Nov. 1998

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