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This paper describes two complementary approaches to performance verification for an MPEG-2 transport demultiplexor. The performance of such devices is difficult to verify during the design phase because of the many independent bus interfaces to which they may be connected and the numerous operating configurations that may be required. To address these problems, we have devised both a pseudorandom verification “environment,” employing “controlled random” simulation, and a hardware-emulation platform based on field-programmable gate arrays (FPGAs). Actual hardware verification has shown the effectiveness of using these two methods together, and the overall approach can be applied to other design programs.
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