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Memory reduction for HDTV decoders

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2 Author(s)
W. -M. Lam ; IBM Research Division, Thomas J. Watson Research Center, P.O. Box 218, Yorktown Heights, New York 10598, USA ; L. Lu

In this paper, we propose a low-cost memory reduction scheme which can reduce the memory requirement for full HDTV decoding from 12 MB to 4 MB. This scheme uses a switchable architecture that allows HDTV decoding with scalable memory reduction ratios. Depending on the input format and the amount of available memory, the scheme performs 1/4 or 1/2 memory reduction or no memory reduction. The 1/2 memory reduction is achieved by performing a block-based Hadamard transform followed by appropriate scalar quantization. The Hadamard transform has good signal energy compaction and a low computational cost. Appropriately designed nonuniform scalar quantizers take advantage of the statistics of the Hadamard transform coefficients and compress the data to match the 1/2 memory reduction target. The 1/4 memory reduction is achieved by 1/2 horizontal decimation followed by the 1/2 memory reduction scheme. Experimental results show that the proposed memory reduction schemes achieve good performance at very low computat ional cost, which makes them very attractive for digital TV applications.

Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.  

Published in:

IBM Journal of Research and Development  (Volume:43 ,  Issue: 4 )