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1 Author(s)
D. A. Buchanan ; IBM Thomas J. Watson, Research Center, USA

Progress in MOS integrated-circuit technology has been largely dominated by the scaling of device feature sizes. For the production of advanced CMOS logic devices with minimum feature sizes in the sub-0.1-µm regime, one of the areas of device fabrication that will limit future CMOS scaling is the continued reduction in the gate dielectric film thickness. This issue of the IBM Journal of Research and Development focuses on the processes and materials that are required to produce reliable CMOS devices with ultrathin gate dielectric films.

Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.  

Published in:

IBM Journal of Research and Development  (Volume:43 ,  Issue: 3 )