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Key measurements of ultrathin gate dielectric reliability and in-line monitoring

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11 Author(s)
W. W. Abadeer ; IBM Microelectronics Division, Burlington facility, Essex Junction, Vermont 05452, USA ; A. Bagramian ; D. W. Conkle ; C. W. Griffin
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High-performance CMOS products depend upon the reliability of ultrathin gate dielectrics. In this paper a methodology for measuring thin gate dielectric reliability is discussed in which the focus is upon the elements of those test structures used in the evaluation, the design of the reliability stress matrix, and the generation of engineering design models. Experimental results are presented which demonstrate the reliability of ultrathin gate dielectrics measured on a wide variety of test structures with dielectric thicknesses ranging from 7 to 3.5 nm. An overview is provided for thin gate oxide reliability that was measured on integrated functional chips—high-performance microprocessors and static random-access memory (SRAM) chips. The data from these measurements spanned the period from early process and device development to full production. Manufacturing in-line monitoring for thin gate dielectric yield and reliability is also discussed, with several case histories presented which show the effectiveness of monitors in detecting process-induced dielectric failures. Finally, causes of oxide fails are discussed, leading to the process actions necessary for controlling thin gate dielectric defects.

Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.  

Published in:

IBM Journal of Research and Development  (Volume:43 ,  Issue: 3 )