Cart (Loading....) | Create Account
Close category search window
 

Key measurements of ultrathin gate dielectric reliability and in-line monitoring

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

11 Author(s)
Abadeer, W.W. ; IBM Microelectronics Division, Burlington facility, Essex Junction, Vermont 05452, USA ; Bagramian, A. ; Conkle, D.W. ; Griffin, C.W.
more authors

High-performance CMOS products depend upon the reliability of ultrathin gate dielectrics. In this paper a methodology for measuring thin gate dielectric reliability is discussed in which the focus is upon the elements of those test structures used in the evaluation, the design of the reliability stress matrix, and the generation of engineering design models. Experimental results are presented which demonstrate the reliability of ultrathin gate dielectrics measured on a wide variety of test structures with dielectric thicknesses ranging from 7 to 3.5 nm. An overview is provided for thin gate oxide reliability that was measured on integrated functional chips—high-performance microprocessors and static random-access memory (SRAM) chips. The data from these measurements spanned the period from early process and device development to full production. Manufacturing in-line monitoring for thin gate dielectric yield and reliability is also discussed, with several case histories presented which show the effectiveness of monitors in detecting process-induced dielectric failures. Finally, causes of oxide fails are discussed, leading to the process actions necessary for controlling thin gate dielectric defects.

Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.  

Published in:

IBM Journal of Research and Development  (Volume:43 ,  Issue: 3 )

Date of Publication:

May 1999

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.