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LSI yield modeling and process monitoring

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1 Author(s)
C. H. Stapper ; System Products Division, Essex Junction, Vermont, USA

This paper describes an analytical technique for quantifying and modeling the frequency of occurrence of integrated circuit failures. The method is based on the analysis of random and clustered defects on wafers with defect monitors. Results from pilot line data of photolithographic defects, insulator short circuits, and leaky pn junctions are presented to support the practicality of the approach. It is shown that, although part of the yield losses are due to the clustering of defects, most product loss is from random failures. The yield model shows good agreement with actual product yields.

Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.  

Published in:

IBM Journal of Research and Development  (Volume:44 ,  Issue: 1.2 )