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Chip integration methodology for the IBM S/390 G5 and G6 custom microprocessors

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16 Author(s)
Averill, R.M., III ; IBM System/390 Division, 522 South Road, Poughkeepsie, New York 12601, USA ; Barkley, K.G. ; Bowen, M.A. ; Camporese, P.J.
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High frequency processor designs operating at more than 500 MHz and of significant architectural complexity require custom physical design constraints from the inception of the design. New technology introductions such as copper interconnect wiring improve performance but also add complexity in ground rules and wiring. A concept known as chip integration, which includes a combination of critical physical design techniques such as floorplanning, power distribution, high-speed clock design, wiring methodologies, circuit macro floorplanning, chip-level timing/extraction, noise prevention, electrical analysis, design verification, and time to market, is given prioritized design consideration throughout all phases of the implementation. This concept is a key requirement necessary to achieve high frequency of operation, meet area targets within the defined architecture, and ensure a robust and reliable design for transistor counts from 10 to 100 million.

Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.  

Published in:

IBM Journal of Research and Development  (Volume:43 ,  Issue: 5.6 )

Date of Publication:

Sept. 1999

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