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1 Author(s)
P. M. Solomon ; IBM Thomas J. Watson Research Center, Yorktown Heights, New York, USA

This issue, “Scaling CMOS to the Limit,” comes at a point in the evolution of CMOS where, on the one hand, the technology has achieved the status of a prime mover of society, the “silicon age,” in which past visions of a dollar per MIPS (million instructions per second) of computer power and a dollar per megabyte of memory have come to pass; while on the other hand the limits of CMOS scaling can be clearly seen. IBM, a prime contributor to this revolution, has seen its computers shrink from the size of a room to a thumbnail-sized chip. This enormous downscaling has been guided, all the while, by the scaling theory of IBM's Robert Dennard. On the other hand, the exponential growth in integrated circuit complexity, which has seen a hundred-millionfold increase in transistor count per chip over the past forty years, is finally facing its limits. Limits projected in the past have seemed to melt away before the concerted efforts of researchers and technologists, yet this time the limits seem more real and already are forcing new strategies on the design of future devices.

Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.  

Published in:

IBM Journal of Research and Development  (Volume:46 ,  Issue: 2.3 )