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The IBM eServer z990 microprocessor

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3 Author(s)
Slegel, T.J. ; IBM Systems and Technology Group, 2455 South Road, Poughkeepsie, New York 12601, USA ; Pfeffer, E. ; Magee, J.A.

The IBM eServer™ z990 microprocessor implements many features designed to give excellent performance on both newer and traditional mainframe applications. These features include a new superscalar instruction execution pipeline, high-bandwidth caches, a huge secondary translation-lookaside buffer (TLB), and an onboard cryptographic coprocessor. The microprocessor maintains zSeries® leadership in RAS (reliability, availability, serviceability) capabilities that include state-of-the-art error detection and recovery.

Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.  

Published in:

IBM Journal of Research and Development  (Volume:48 ,  Issue: 3.4 )