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Using microcode in the functional verification of an I/O chip

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3 Author(s)
S. P. Goldman ; IBM Systems and Technology Group, 2455 South Road, Poughkeepsie, New York 12601, USA ; L. M. Mohr ; D. R. Smith

The IBM pSeries® clustered and parallel processing systems require high-speed, low-latency communication among processor nodes. The 2-Link Switch Network Interface and 4-Link Switch Network Interface for the pSeries High Performance Switch are the adapters which provide the communication infrastructure for the pSeries p655 and p690 servers. A unique approach was used during the functional verification of these adapters that yielded benefits over the methodology used for the previous-generation product—the SP™ Switch2 Adapter. The approach used on the Switch Network Interface introduced the concept of using microcode during the functional verification process. This paper gives an overview of functional verification, followed by a description of the SP Switch2 Adapter and the Switch Network Interface. The verification methodologies used on these adapters are described and compared. Finally, the benefits of implementing hardware/software co-verification on the Switch Network Interface throughout the development cycle are described.

Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.  

Published in:

IBM Journal of Research and Development  (Volume:49 ,  Issue: 4.5 )