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Optimizing CMOS technology for maximum performance

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4 Author(s)
Frank, D.J. ; IBM Research Division, Thomas J. Watson Research Center, P.O. Box 218, Yorktown Heights, New York 10598, USA ; Haensch, W. ; Shahidi, G. ; Dokumaci, O.H.

Since power dissipation is becoming a dominant limitation on the continued improvement of CMOS technology, technologists must understand the best way to design transistors in the presence of power constraints. The primary objective is to obtain as much performance as possible for a fixed amount of power, and it is chip performance, not device performance, that matters. In order to investigate this regime, we have captured in simplified models the basic elements for determining chip performance, including intrinsic transistor characteristics, circuit delay, tolerance issues, basic microprocessor composition, and power dissipation and heat removal considerations. These models have been assembled in a processor-level technology-optimization program to study the characteristics of optimal technology across many generations of CMOS. The results that are presented elucidate the limits of future CMOS technology improvements, the optimal energy consumption conditions, and the relative benefits of various proposed technology enhancements, including high-k gate insulators, metal gates, high-mobility semiconductors, improved heat removal, and the use of multiple layers of circuitry.

Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.  

Published in:

IBM Journal of Research and Development  (Volume:50 ,  Issue: 4.5 )

Date of Publication:

July 2006

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