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Soft-error resilience of the IBM POWER6 processor

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9 Author(s)
P. N. Sanda ; IBM Systems and Technology Group, 2455 South Road, Poughkeepsie, New York 12601, USA ; J. W. Kellington ; P. Kudva ; R. Kalla
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The error detection and correction capability of the IBM POWER6™ processor enables high tolerance to single-event upsets. The soft-error resilience was tested with proton beam- and neutron beam-induced fault injection. Additionally, statistical fault injection was performed on a hardware-emulated POWER6 processor simulation model. The error resiliency is described in terms of the proportion of latch upset events that result in vanished errors, corrected errors, checkstops, and incorrect architected states.

Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.  

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IBM Journal of Research and Development  (Volume:52 ,  Issue: 3 )