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New and effective modeling methodologies have been developed to simulate particle transport in arbitrarily complex back-end-of-line (BEOL) topologies of a semiconductor chip. They are applied to address a number of critical problems that involve the single-event-effect analysis of new device structures for 65-nm CMOS (complementary metal-oxide semiconductor) technologies and beyond. These new simulation techniques also provide a generic building block on which a new version of the IBM soft-error Monte Carlo model (SEMM-2) is constructed. In this paper, we review the basic concepts of this development and discuss some important applications.
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