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Structural and functional test of IBM System z10 chips

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14 Author(s)
Salem, G. ; IBM Systems and Technology Group, 1000 River Street, Essex Junction, Vermont 05452, USA ; Wittig, D.W. ; Foote, T.G. ; Robbins, B.J.
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For the first time in the history of the IBM System z™ family of mainframes, System z10™ processor chips are tested by both structural and functional means. This complementary strategy starts at wafer test and is consistent through system test. In this paper, we describe how traditional and enhanced structured patterns provide fault coverage and how functional patterns mimic real system workloads. A new operating kernel generates functional tests and expected results and it can run these tests for either a finite or an indefinite amount of time to simulate system operation. It also executes custom hand-loop patterns to stress chip temperature and power. Both structural and functional patterns are used to uniquely characterize each chip. Adaptive algorithms based on results at wafer test determine optimal system operating voltage for each chip—a strategy that delivers a chip supply with optimal characteristics for system manufacturing and product delivery. The diversity of structural and functional patterns makes it possible to increase z10™ chip quality and reduce development time. The ability to run the same tests from wafer through system test provides a consistency not previously possible.

Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.  

Published in:

IBM Journal of Research and Development  (Volume:53 ,  Issue: 1 )