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Analysis of the control loop of clock-data recovery circuits (CDR) that use bang-bang phase detector is complicated by the fact that the loop behavior is determined by the jitter profile of the input signal. We present a method for constructing a non-linear average deviation model that permits fast simulation of the limit cycle behaviors. In addition, linear AC analysis performed on the model allow observing the control loop transfer functions. The main idea is to model the average behavior of the non-linear phase detector using the cumulative density function (CDF) of the total jitter. The random jitter (RJ) component is assumed Gaussian and the deterministic jitter (DJ) is modeled using a histogram approach. The total jitter CDF is obtained by convolving the RJ and DJ components. For ease of implementation in VerilogA, we use a polynomial approximation for the Gaussian CDF. Finally we present simulation results that show correlation with the long time consuming full circuit simulations.