By Topic

Designing analog and RF circuits in nanoscale CMOS technologies: Scale the supply, reduce the area and use digital gates

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Kinget, P. ; Dept. of Electr. Eng., Columbia Univ., New York, NY, USA

We will present our recent research that has centered around three themes aimed at facilitating the design of analog and RF interface circuits in digital nanoscale CMOS processes. Nanometer CMOS is operating with supply voltages of about 1 V or less and for low power operation in future deeply scaled nodes supply voltages as low as 0.5 V are projected. Supply reductions are needed to maintain reliability for scaled devices, but are further strongly driven by the requirement to improve energy efficiency, so that functional density can increase without raising power density. In our research we have investigated the scaling of the supply voltage of analog and RF interfaces down to 0.5 V. Keeping these interfaces compatible with the core digital technology and supply is eventually always preferred for high volume applications and can offer advantages in low power system-on-chip applications with large digital signal processing cores. We will show that this research track offers ample opportunities for innovations in device biasing, circuit topologies, system architectures and signaling. Our ultra-low voltage prototypes include reference circuits, filters, analog-to-digital converters and fully integrated RF front-ends including baseband filtering and frequency synthesis. A second important theme is circuit design techniques to reduce area used by RF integrated circuits. Recent RFIC designs rely substantially on the use of on-chip spiral inductors, but these structures do not scale sufficiently with technology and become progressively more expensive. We will show design and layout techniques that allow to reuse the space under spiral inductors without affecting the performance of the building blocks. Examples include voltage-controlled oscillators and fully integrated phase-locked loops. Finally we will discuss the use of digital gates to improve the performance of analog and RF integrated circuits. Digital signal processing blocks are reducing much faster in area and po- wer than analog or RF circuits and whenever possible the assistance of digital computation should be exploited to reduce the need for analog/RF circuits or enhance their performance. In particular we will discuss the opportunities for using digital intelligence to improve the linearity performance of RF front-ends while making them more robust to process variations and simplifying their design. We will point out the need for a different approach for digital assistance for RF functions compared to mixed signal functions.

Published in:

Microwaves, Communications, Antennas and Electronics Systems, 2009. COMCAS 2009. IEEE International Conference on

Date of Conference:

9-11 Nov. 2009