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Traditional pulse-width modulation (PWM) in a DC-DC converter offers high efficiency but has large spurs occurring at integer multiples of the clock frequency. An alternate architecture using the delta sigma (Â¿Â¿) controller is studied and compared for theoretical spurious performance and efficiency. Tradeoffs in selecting the delta-sigma order, over sampling ratio (OSR), and input voltage (Vin) range are investigated. While a large OSR and high order can reduce the magnitude of the spurs and push them out to a higher frequency, the power efficiency of the system is compromised. This paper aids designers in exploring the design space for the optimal Â¿Â¿ parameters given efficiency and spurious performance specifications.