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Capacitance variation under electrical stress of SiOCH low-k dielectrics for the advanced 45nm technology node and beyond

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5 Author(s)
M. Vilmay ; STMicroelectronics, 850 rue Jean Monnet 38926 Crolles, France ; D. Roy ; S. Blonkowski ; F. Volpi
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Porous low-k dielectrics reliability in interconnect is a major concern for sub 45 nm technology nodes. Low-k dielectric ageing characterization during stress is becoming a key point to improve low-k interconnect robustness. In this context, the leakage and especially the capacitance shifts under electrical stress are analyzed in this paper. Four dielectric ageing mechanisms potentially responsible of the capacitance drift during stress are discussed and compared to experiments. Donor trap creation leading to the I(V) sweep variation is confirmed with leakage activation energy measurement during the stress. Moreover, the capacitance shift could be due to a trapping/detrapping charge into pre-existing or created traps.

Published in:

2009 IEEE International Integrated Reliability Workshop Final Report

Date of Conference:

18-22 Oct. 2009