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For the demand of multi-function and higher performance in electronic devices, the three-dimensional chip stacking technology with fine pitch and high input/output (I/O) interconnections has emerged recently. In addition, with the joint size becoming smaller, the current that each solder bump carried continues to increase, resulting in high current flowing in each individual joint. Therefore, electromigration has become a major reliability issue in microelectronic devices. In this study, a chip-on-chip test vehicle with a bump pitch of 30μm was adopted to evaluate the bonding feasibility and electromigration resistance of micro bump interconnections. There were more then 3000 micro bumps with Sn2.5Ag solder material on both the silicon chip and silicon carrier. Two types of under bump metallurgy layer (UBM) on the Si chip/carrier were selected in this study. One was single copper layer with a thickness of 8 μm and the other was Ni/Cu layer with a total thickness of 8 μm. Different temperatures, times and pressures of thermo-compression bonding conditions were considered to obtain the optimization of bonding parameter. The 3D chip stacking using two layers of chip with fine pitch and lead-free interconnects was achieved in this study. Electromigration of micro bump interconnections in the joint structure of Cu/Ni/SnAg was investigated. Finite element analysis (FEA) was also employed to determine the current distribution in the solder joint. The results of electromigration test showed that the electromigration lifetime was well correlated with the bump microstructure.