Cart (Loading....) | Create Account
Close category search window
 

Design and Implementation of a Configurable Interleaver/Deinterleaver for Turbo Codes in 3GPP Standard

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)

During the last decade, Turbo codes have been taking an increasing importance in channel coding due to its good performance in error correction. One key component in Turbo codes is the interleaver/deinterleaver pair, often designed as reconfigurable coprocessors able to deal with requirements of large data length variability found in the newest communication standards. In this work we introduce a configurable interleaver architecture for the turbo decoder in 3rd Generation Partnership Project (3GPP) standard. It is implemented under the idea of ¿iterative modulo computation¿. Additionally, the presented solution not only generates the interleaved addresses, but also deals with the flow of data streams through the interleaver. The architecture and FPGA implementation results are also presented.

Published in:

Reconfigurable Computing and FPGAs, 2009. ReConFig '09. International Conference on

Date of Conference:

9-11 Dec. 2009

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.