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A New CLB Architecture for Tolerating SEU in SRAM-Based FPGAs

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2 Author(s)
Alireza Rohani ; Dept. of Comput. Eng. & Inf. Technol., Amirkabir Univ. of Technol., Tehran, Iran ; Hamid R. Zarandi

This paper proposes a new reconfigurable architecture for configuration logic block (CLB) in SRAM-based FPGAs. This architecture can correct single event upset (SEU) by utilizing both triple modular redundancy (TMR) and mapping technique. Since the proposed architecture can implement all the k-input Boolean functions, it can be used instead of look-up table (LUT) in current-day SRAM-based FPGAs; moreover, the proposed architecture uses the same routing architecture which is presented in current-day FPGAs, so all CAD algorithms can be used in the employed design. Experimental results show that the proposed architecture can correct 100% SEU in the configuration memory of CLB without any user intervention or reconfiguration; moreover, the required area and the power consumption are respectively 136% and 195% more than the area and the power consumption that are required by the standard 16×1 LUT.

Published in:

2009 International Conference on Reconfigurable Computing and FPGAs

Date of Conference:

9-11 Dec. 2009