By Topic

Implementation of a Dynamic Fault-Tolerance Scaling Technique on a Self-Adaptive Hardware Architecture

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Soto, V.J. ; Dept. of Electron. Eng., Tech. Univ. of Catalunya (UPC), Barcelona, Spain ; Moreno, J.M. ; Madrenas, J. ; Cabestany, J.

The purpose of this paper is to describe a dynamic fault tolerance scaling technique that is supported by the self-adaptive features of a hardware architecture developed within the framework of the AETHER project. The architecture is composed of an array of cells that support dynamic and distributed self-routing and self-placement of components in the system. The combination of a large array of cells together with component-level routing ultimately constitutes a SANE (self-adaptive networked entity). The dynamic fault tolerance scaling technique proposed in this paper permits a given subsystem to modify autonomously its structure in order to achieve fault detection and fault recovery. The decision to modify or not its organization is based on the actual power consumption of the system.

Published in:

Reconfigurable Computing and FPGAs, 2009. ReConFig '09. International Conference on

Date of Conference:

9-11 Dec. 2009