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A 0.6v Ultra-High-Gain Ultra-Low-Power CMOS LNA at 1.5GHz in 0.18µm Technology

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3 Author(s)
Kargaran, E. ; Sadjad Inst. for Higher Educ., Mashhad, Iran ; Kargaran, H. ; Nabovati, Hooman

This paper describes a CMOS LNA utilizing a folded cascade architecture for GPS front-end receiver in a TSMC 0.18-μm process. The major problem in the LNAs with folded cascade architecture is low reversing isolation. In this paper this parameter is improved by adding a transistor. The power gain and the minimal noise figure (NF) are two important factors for the circuits. Besides those factors, good linearity, input impedance matching, low supply voltage and the lower power consumption are also desired. The proposed LNA achieves a small signal gain of 23.1 dB. The LNA acquires an NF of 2.1 dB with an input return loss of -14dB and an output return loss of -14 dB. Total power consumption is only 2.6mW from a 0.6v supply voltage.

Published in:

Computer and Electrical Engineering, 2009. ICCEE '09. Second International Conference on  (Volume:1 )

Date of Conference:

28-30 Dec. 2009

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