By Topic

Design of SOI FinFET on 32 nm technology node for low standby power (LSTP) operation considering gate-induced drain leakage (GIDL)

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

6 Author(s)
Seongjae Cho ; Sch. of Electr. Eng. & Comput. Sci., Seoul Nat. Univ., Seoul, South Korea ; Jung Hoon Lee ; O'uchi, S. ; Endo, K.
more authors

Recently, minimizing the standby power is considered as a critical issue in high-density, mobile CMOS technology. One of the major sources of the leakage current in off-state of ultra-small MOSFET is gate-induced drain leakage (GIDL) which is mainly composed of inter-band and trap-assisted tunneling. By virtues of reduced intra-junction and punch-through leakage currents, threshold voltage controllability, and higher current drivability, SOI FinFETs are utilized in most recent CMOS circuits. In this work, half-pitch (HP) 32 nm SOI FinFETs are designed for LSTP considering GIDL by device simulation with regard to junction doping profile. For more accurate results, various models for carrier mobility, gate current, recombination, band-to-band and trap-assisted tunneling, and quantum effects have been activated.

Published in:

Semiconductor Device Research Symposium, 2009. ISDRS '09. International

Date of Conference:

9-11 Dec. 2009