Electron trapping at interface states in SiO2/4H-SiC and SiO2/6H-SiC MOS capacitors

The SiO
₂
/SiC interface limits optimum SiC MOSFET performance due to a high density of interface states (D
_¿¿
), which is reduced in devices that receive post-oxidation NO-annealing. Also, the interface state density in the 6H polytype is generally lower, approaching that of the NO treated 4H. In this work, interface states are investigated in both as-oxidized (AO) and NO-annealed (NO) MOS capacitors fabricated from n-type epitaxial (0001) 4Hand 6H-SiC. Oxidation was done in dry O
₂
at 1150°C followed by 30 min in Ar ambient. The NO exposure was at 1175°C for 2h. Constant capacitance deep level transient spectroscopy (CCDLTS) results are compared with the D
_¿¿
from hi-lo C-V and temperature dependent C-V measurements.