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Electron trapping at interface states in SiO2/4H-SiC and SiO2/6H-SiC MOS capacitors

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7 Author(s)
Basile, A.F. ; Simon Fraser Univ., Burnaby, BC, Canada ; Rozen, J. ; Chen, X.D. ; Dhar, S.
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The SiO2/SiC interface limits optimum SiC MOSFET performance due to a high density of interface states (D¿¿), which is reduced in devices that receive post-oxidation NO-annealing. Also, the interface state density in the 6H polytype is generally lower, approaching that of the NO treated 4H. In this work, interface states are investigated in both as-oxidized (AO) and NO-annealed (NO) MOS capacitors fabricated from n-type epitaxial (0001) 4Hand 6H-SiC. Oxidation was done in dry O2 at 1150°C followed by 30 min in Ar ambient. The NO exposure was at 1175°C for 2h. Constant capacitance deep level transient spectroscopy (CCDLTS) results are compared with the D¿¿ from hi-lo C-V and temperature dependent C-V measurements.

Published in:

Semiconductor Device Research Symposium, 2009. ISDRS '09. International

Date of Conference:

9-11 Dec. 2009

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